Regviz

Silicon Labs /BGM240PB32VNN /GPIO_S /EUSART0_ROUTEEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as EUSART0_ROUTEEN

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32MG24A120F1536GM48/GPIO_NS/EUSART0_ROUTEEN#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSPEN)CSPEN 0 (RTSPEN)RTSPEN 0 (RXPEN)RXPEN 0 (SCLKPEN)SCLKPEN 0 (TXPEN)TXPEN

Description

EUSART0 pin enable

Fields

CSPEN

CS pin enable control bit
RTSPEN

RTS pin enable control bit
RXPEN

RX pin enable control bit
SCLKPEN

SCLK pin enable control bit
TXPEN

TX pin enable control bit

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data